The present invention relates generally to layouts in very large scale integrated (VLSI) circuits and, more particularly, to a method for implementing overlay-based modification of VLSI design layouts.
It is sometimes desirable to modify the final layout of a completed VLSI physical design to obtain better yield and/or electrical performance. For instance, in complementary metal oxide semiconductor (CMOS) devices having n-type and p-type transistors, it has been discovered that the conductivity (and hence performance) of each type of transistor is improved when layers of opposing mechanical stress (e.g., compressive versus tensile) are formed over each. In order to form “strained silicon” layers of this type, ground rule changes may be needed for certain geometric features such as the amount of overlap of doped well regions with respect to diffusion regions or with respect to gate contact regions, for example.
In situations where such layout modifications are done late in the design cycle, these modifications should be implemented in a low-risk fashion, and as unobtrusively as possible. On one hand, the manual modification of layouts is very time consuming. In addition, changes to library cells that are used many hundreds or even thousands of times must be made in such a way that the modified cell is still ground-rule correct in every environment in which the cell is used. Also, it is often not possible to modify library cells late in the design cycle. As a result, there is presently little benefit to be gained by optimizing shapes in situ.
Accordingly, it would be desirable to be able to implement layout modifications for a cell in a manner that is independent of the specific uses for such a cell, that allows for the original layout data to be unchanged, and that is substantially invisible with respect to the design tools used in the process flow.